Product Main Title:
LS0144T10-M-V1: 1.44-Inch TFT LCD Module, 128x128 Resolution, 262K Colors, 8-bit 8080 Parallel Interface, NV3023B Driver
Product Subtitle / Keywords:
1.44 Inch TFT Display, 128x128 Resolution, Transmissive a-Si TFT, 8-bit 8080 Parallel MCU Interface, COG+FPC+B/L, 262K Colors, Parallel Timing, Multi-function Control Pins
Comprehensive Technical Specification & Application Guide
1. Executive Summary & Product Positioning
The LS0144T10-M-V1, developed by LESSON (Wan'an) Zhixian Technology Co., Ltd., is a 1.44-inch transmissive a-Si TFT-LCD module distinguished by its 8-bit 8080-series parallel microprocessor interface. This product specification book provides the definitive technical definition, covering its structural composition, mechanical dimensions, absolute maximum ratings, detailed electrical characteristics, and comprehensive parallel interface timing specifications. It delivers a resolution of 128(RGB)×128 with 262K-color capability, driven by the NV3023B controller. This module is designed for applications where a parallel data bus is preferred or required for higher data throughput compared to serial interfaces. Engineers should leverage this document specifically for the parallel interface pin functions, timing parameters, and initialization procedure to ensure correct communication with the host MCU.
2. Detailed Product Overview & Architecture
- Core Technology: Transmissive-type a-Si TFT-LCD.
- Display Characteristics: Capable of displaying up to 262K colors.
- Module Construction: Composed of a TFT-LCD panel, a driver circuit, and a backlight unit.
- Interface: 8-bit 8080 parallel interface. Input data format is 8-bit.
- Driver IC: NV3023B.
- Viewing Direction: TN (Twisted Nematic).
3. Exhaustive Technical Specifications
3.1 Mechanical & Physical Specifications
- Panel Size (Diagonal): 1.44 inches
- Active Area (H×V): 25.5 mm × 26.5 mm
- Module Size (H×V×D): 29.00 mm × 34.41 mm × 2.2 mm
- Resolution: 128 (RGB) × 128 pixels
- Display Format: Graphic 128(RGB)×128 Dot-matrix
3.2 Electrical & Interface Specifications
3.2.1 Absolute Maximum Ratings
| Item | Symbol | Min | Max | Unit | Remark |
|---|---|---|---|---|---|
| Supply voltage | VCC | -0.3 | 4.8 | V | Note1,2 |
| I/O Supply voltage | IOVCC | -0.3 | 3.6 | V | Note1,2 |
| Operating temperature | TOPR | -20 | 70 | °C | Note1,2 |
| Storage temperature | TSTR | -30 | 80 | °C | Note1,2 |
3.2.2 Electrical Characteristics (DC, Ta=25°C)
| Item | Symbol | Min | Typ | Max | Unit | Remark |
|---|---|---|---|---|---|---|
| Supply voltage (Main) | VCC | 2.5 | 2.75 | 4.8 | V | |
| I/O Supply voltage | IOVCC | 1.65 | 1.8 | 3.6 | V | |
| Input Voltage (L) | VIL | 0 | -- | 0.3*IOVCC | V | |
| Input Voltage (H) | VIH | 0.7*IOVCC | -- | IOVCC | V |
3.2.3 Pin Description (24-pin FPC) - Parallel Interface Focus
| PIN NO. | Symbol | I/O | Description |
|---|---|---|---|
| 1 | VDD | P | Power supply |
| 2 | GND | P | Ground |
| 3 | NC | Not Connected | |
| 4 | TE | O | Tearing effect output pin |
| 5 | CS | I | Chip Select Pin ("Low Active") |
| 6 | RS | I | Multi-function Pin: MCU I/F: Data('1')/Command('0'); SPI I/F: SCL clock. |
| 7 | RD | I | 8080-parallel: 'Read' enable. |
| 8 | WR | I | Multi-function Pin: 8080-parallel: Write enable; SPI 4-wire: D/CX; 2-Line SPI: Data input. |
| 9 | RESET | I | Reset |
| 10, 12, 14, 16, 18, 20, 22, 24 | D0-D7 | I | 8-bit data bus (D0...D7) |
| 11, 13, 15, 17, 19, 21, 23 | NC | Not Connected (between data lines) |
Key Interface Note: Pins 6 (RS) and 8 (WR) have multiple functions depending on the configured interface mode. This specification focuses on the 8-bit 8080 parallel mode, where RS is D/CX, RD is read strobe, and WR is write strobe.
3.2.4 Critical Interface Timing
A. Reset Timing:
| Symbol | Parameter | Related Pins | MIN | TYP | MAX | Note | Unit |
|---|---|---|---|---|---|---|---|
| t_RW | Reset low pulse width | RESX | 10 | - | - | - | us |
| t_RT | Reset Complete time | RESX | - | - | 5 | Sleep-in mode | ms |
| t_RT | Reset Complete time | RESX | - | - | 120 | Sleep-out mode | ms |
B. 8080 Parallel Interface AC Characteristics (Asynchronous Mode): Extensive timing parameters are provided:
- Control Signals: Address setup/hold (
T_AST,T_AHT), Chip Select setup/hold/pulse width (T_CS,T_CSH,T_CHW), Write cycle/pulse widths (T_WC,T_WRH,T_WRL), Read cycle/pulse widths (T_RC,T_RDH,T_RDL). - Data Bus: Data setup/hold (
T_DST,T_DHT), Read access time (T_RAT), Output disable time (T_ODH). - Example Values:
T_WCmin 80 ns,T_RCmin 160 ns (Read ID),T_DSTmin 10 ns.
3.2.5 Backlight Unit
Information not explicitly detailed in provided excerpts, but consistent with similar 1.44" models (likely 2-chip LED, If=40mA).
3.3 Optical & Electro-Optical Characteristics (Ta=25°C)
| Item | Symbol | Condition | Min. | Typ. | Max. | Unit | Remark |
|---|---|---|---|---|---|---|---|
| Response Time | Tr + Tf | θx=θy=0 | - | 25 | 30 | ms | |
| Contrast Ratio | CR | θx=θy=0 | 300 | 600 | - | - | |
| Transmittance | T% | θx=θy=0 | 3.9 | 5.5 | - | % | |
| Viewing Angle (CR>10) | θT | - | - | 70 | - | Deg. | |
| Viewing Angle (CR>10) | θB | - | - | 60 | - | Deg. | |
| Viewing Angle (CR>10) | θL, θR | - | - | 75 | - | Deg. | |
| Color Chromaticity (White) | W x, W y | θx=θy=0 | - | 0.301, 0.327 | - | - |
4. Application Guidelines & Critical Notes
- Intended Use: Applications where the host microcontroller has an available parallel bus or requires higher display update speeds than SPI can provide. Common in older or specific MCU architectures.
- Critical Design Considerations:
- Parallel Bus Resource Intensive: This interface requires up to 11 GPIOs (8 data + CS, RS, WR, RD) from the host MCU, plus RESET. Ensure your MCU has sufficient pins.
- Interface Mode Configuration: The module likely supports multiple interfaces (Parallel, SPI). Ensure it is configured or wired for 8080 parallel mode. The pin description suggests this is the primary mode for this variant.
- Timing Generation: The host must generate the WR, RD, and CS strobes with precise timing relative to the data on D0-D7 and the RS signal. Carefully review all AC characteristics.
- Bus Contention: Manage the data bus direction correctly. The data pins are input-only for the host during writes. Read timing is also provided if needed.
- Unused Pins: Many pins are marked NC (Not Connected). Do not connect them in your design.
- Power Supply: Provide stable 2.75V (VCC) and 1.8V (IOVCC) supplies.
- Handling: Standard ESD precautions.
5. Conclusion & Design-In Support
The LS0144T10-M-V1 specification details a 1.44-inch display module with a traditional 8-bit 8080 parallel interface, setting it apart from the more common SPI-based variants. Its key feature is the comprehensive parallel timing specification, enabling direct connection to microprocessors with a memory-mapped peripheral bus. This interface can offer performance benefits for full-frame updates. The design challenge lies in the significant number of GPIO pins required and the need for the host to generate compliant bus timing. Engineers should thoroughly study the AC characteristic tables to ensure their MCU or FPGA can meet the setup, hold, and pulse width requirements. This module is an ideal choice when SPI bandwidth is insufficient and parallel port resources are available.
