LS089I02-MP-V1: 8.9-Inch WQXGA TFT LTPS Display Module, 2560×1600 Resolution, MIPI Interface, Ultra-Fine Pixel Pitch

LS089I02-MP-V1: 8.9-Inch WQXGA TFT LTPS Display Module, 2560×1600 Resolution, MIPI Interface, Ultra-Fine Pixel Pitch

Product Subtitle / Keywords

8.9 Inch Display, 2560*RGB*1600 WQXGA Resolution, LTPS (Low Temperature PolySilicon) TFT Panel, IPS/Transmissive Display Mode, 16.8M Display Colors, Viewing Angle 80/80/80, Contrast Ratio 1200:1 (Typ), NTSC 72% (Typ), Ultra-Fine Pixel Pitch 75*75 µm, Panel Active Area 192.0(W) x 120.0(H) mm, FOG Size 197.60 x 129.60 x 0.749 mm, Glass Thickness 0.25/0.25 mm, Driver IC R69429*2, MIPI 8-Lane 2-Port Video Mode Interface, Operating Temperature -20~60°C, Storage Temperature -30~70°C, Lesson Smart Display Technology Co., Ltd.

1. Executive Summary & Product Positioning

The LS089I02-MP-V1, developed by Lesson Smart Display Technology Co., Ltd. (立信(万安)智显科技有限公司), is an 8.9-inch WQXGA TFT LTPS (Low Temperature PolySilicon) display panel. The specification, dated 2014-05-23 (Version 0.1), details its general specifications, DC characteristics, current consumption, interface pin assignment (MIPI), and timing restrictions for video mode.

This product specification serves as the definitive technical document, defining the module's ultra-high resolution (2560×1600), advanced LTPS backplane technology, MIPI DSI interface (8 Lane, 2 Port), and power supply requirements. The unequivocal recommendation for engineers is to strictly adhere to the multi-rail power supply voltages (IOVCC, DPHYVCC, VSP, VSN) and the meticulous MIPI timing restrictions described herein to ensure reliable performance and optimal display quality.

2. Detailed Product Overview & Architecture

• Core Technology: TFT LTPS (Low Temperature PolySilicon) panel. LTPS technology offers higher electron mobility than standard a-Si, enabling higher resolution and smaller bezels.
• Display Resolution: WQXGA: 2560*RGB*1600 pixel array.
• Display Mode: IPS (In-Plane Switching) / Transmissive, providing wide viewing angles and accurate color reproduction.
• Interface Type: MIPI 8Lane 2Port (Mobile Industry Processor Interface, 8 data lanes configured as 2 ports) in Video Mode.
• Display Colors: Up to 16.8M colors (8-bit + FRC).
• Power Architecture: Requires a quad-rail power supply: I/O Logic (IOVCC=1.8V), DPHY (DPHYVCC=1.8V), Positive Analog (VSP=5.5V), and Negative Analog (VSN=-5.5V).
• Driver IC: Uses dual R69429 driver ICs, one serving as Master and one as Slave.

3. Exhaustive Technical Specifications

3.1 Mechanical & Physical Specifications

3.2 Electrical & Interface Specifications

3.2.1 DC Characteristics

3.2.2 Current Consumption

Note: In sleep mode, all internal display operations are suspended except for the internal R-C oscillator.

3.2.3 Interface Pin Assignment (LCM Connector)

The module features a connector with the following key pins for power and MIPI signals:

Note: The above list includes the pins visible from the provided snippet. The full pinout includes additional MIPI data lanes (e.g., MIPI_1N_B, MIPI_1P_B, MIPI_2N_B, MIPI_2P_B, MIPI_CKP_B), MIPI lanes for Port A, and additional GND pins. The “B” suffix in some signal names indicates a second MIPI port, consistent with the 2-Port interface description.

3.3 MIPI DSI Timing & Video Mode Restrictions

The specification includes critical timing parameters for the MIPI interface, particularly regarding the transition between Command Mode and Video Through Mode.

• DSI Clock Frequency: When fDSICLK < 125MHz, an auto load NV setting must be changed to be compliant with the THS-PREPARE + THS-ZERO timing specification.
• Setup/Hold Time: The minimum tSETUP/tHOLD Time is 0.15 UI (Unit Interval). This value may change according to the DSI transfer rate and is measured without HS-TX Jitter.
• Mode Switching: The timing diagram shows the interaction between TE (Tearing Effect) signal and the switching between Command Mode and Video Through Mode. Key timing notes include:
  • Send video mode command when TE rises up.
  • Send command mode command when TE rises up (when switching back).
  • Command mode will be off from the next Vsync packet input.
  • Command mode will start from the next frame timing.
• Video Mode Blanking Restriction: The blanking period is specified for pixel data transfer to the two chips (Master & Slave) in Video Mode. The time that the pixel data transfer to the slave chip precedes and is behind the pixel data transfer to the master chip must be set to 45 ByteClock or less.

3.4 Cross Talk Definition

The spec defines Cross Talk (CT) as the luminance differences between adjacent areas around a window. The formula for calculating crosstalk is:

Cross-talk = |Wi' - Wi| / Wi × 100(%)

Where Wi' is the luminance of an area when a window is present, and Wi is the luminance of the same area without the window.

4. Application Guidelines & Critical Notes

Intended Use

• High-resolution 8.9-inch display applications requiring WQXGA (2560×1600) resolution.
• Systems utilizing a high-speed MIPI DSI interface with 8 lanes configured as 2 ports (4 data lanes per port).
• Applications requiring a premium IPS display with wide viewing angles (80/80/80), high contrast (1200:1), and wide color gamut (72% NTSC).
• Ultra-slim device designs leveraging the thin glass profile (0.749 mm FOG thickness).

Critical Design Considerations

1. MIPI DSI Interface Configuration (8-Lane, 2-Port): This is the most critical interface aspect. The module uses an 8-lane MIPI DSI interface configured as two separate ports (Port A and Port B), each with 4 data lanes. The host processor must be capable of driving 8 data lanes and one clock lane per the MIPI DSI specification. The spec shows signals like MIPI_0N_B to MIPI_3N_B (Port B), implying a similar set for Port A.
2. Quad-Rail Power Supply: The module requires four separate, tightly regulated power supplies:
   • IOVCC (1.8V): For I/O interface logic.
   • DPHYVCC (1.8V): For the MIPI D-PHY block (must be connected to IOVCC).
   • VSP (+5.5V): Positive analog supply for the driver IC.
   • VSN (-5.5V): Negative analog supply for the driver IC.
   A dedicated PMIC or multiple DC-DC converters with low ripple are necessary for all four rails.
3. Master/Slave Driver IC Setup: The module uses dual R69429 driver ICs, one designated as Master and one as Slave. The video data must be transmitted to both chips simultaneously, and the blanking period between the data transfers must be ≤ 45 ByteClock.
4. Ultra-High Resolution (2560×1600) and Frame Rate (60Hz): This resolution requires a very high MIPI data rate. The total pixel clock can be calculated as: 2560 × 1600 × 60 Hz = 245.76 MHz. With 8 lanes, each lane must operate at a bit rate of approximately (245.76 × 24 bits/pixel) / 8 lanes ≈ 737.28 Mbps. The host DSI transmitter must support this high data rate.
5. TE (Tearing Effect) Signal Management: The module uses a TE signal to synchronize mode switching between Command Mode and Video Mode. The host must respond to the TE rising edge to send the appropriate mode commands.
6. Ultra-Slim Module Profile: The FOG (FPC on Glass) thickness is only 0.749 mm. This requires careful mechanical design and handling to avoid glass breakage. The glass thickness is a mere 0.25 mm per sheet.
7. LTPS Technology vs. a-Si: This module uses an LTPS TFT backplane, which offers higher electron mobility. This allows for the very high resolution and pixel density (75µm pixel pitch). The driver IC and interface requirements are different from a standard a-Si module.
8. Cross Talk Performance: The specification provides a definition for Cross Talk (CT), which is a measure of luminance uniformity around contrasting patches. System integrators should ensure that backlight uniformity and driving conditions do not exacerbate this effect.

Handling & Compliance

• Observe standard ESD precautions during handling and assembly.
• The module is extremely fragile due to its thin glass (0.25 mm top/bottom) and overall thin profile. Extreme care must be taken during handling, mounting, and FPC connection.
• Avoid any pressure or point loads on the active display area.
• Do not attempt to disassemble or modify the LCD module.
• All NC (No Connection) pins should be left open.
• The specification is marked as Version 0.1 (Draft). Contact the manufacturer for the final, approved specification before production deployment.

5. Conclusion & Design-In Support

The LS089I02-MP-V1 specification details a highly advanced 8.9-inch WQXGA LTPS TFT display module with an 8-lane MIPI DSI interface, dual-driver IC architecture, and exceptional optical performance — a cutting-edge choice for premium tablets, high-end portable devices, and demanding embedded display applications requiring the highest resolution in a compact form factor.

Key Strengths

• Ultra-High Resolution (2560×1600 WQXGA): Exceptional pixel density and image clarity.
• LTPS Backplane Technology: Enables high resolution, narrow bezel, and low power consumption.
• IPS Display Mode: Wide viewing angles (80/80/80) and high contrast ratio (1200:1).
• 8-Lane MIPI DSI (2-Port): High bandwidth interface capable of driving the high-resolution panel at 60 Hz.
• Wide Color Gamut (72% NTSC): Vibrant and accurate color reproduction.

Main Design Focus

• The critical design tasks are implementing the quad-rail MIPI power supply (IOVCC=1.8V, DPHYVCC=1.8V, VSP=+5.5V, VSN=-5.5V) and configuring the host's MIPI DSI transmitter for an 8-lane, 2-port configuration capable of driving WQXGA (2560×1600) resolution at a 60 Hz frame rate.
• Supporting requirements: Manage the TE signal for correct mode switching. Design the mechanical housing to accommodate the extremely thin module profile (0.749 mm FOG thickness) and protect the fragile glass. Ensure that the blanking period between master and slave data transfers does not exceed 45 ByteClock.

This module is a premium choice for the most demanding engineers requiring a state-of-the-art, high-resolution 8.9-inch display based on advanced LTPS technology and a high-speed MIPI interface.