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LSC101I35-MP-V2 10.1 inch TFT-LCD Module 800x1280 16.7M Colors IPS driver IC JD9365DA-H3 MIPI (4 Data Lane) Interface

LSC101I35-MP-V2 10.1 inch TFT-LCD Module 800x1280 16.7M Colors IPS

Product Keywords: 10.1″ LCD Module with CTP, COG+FPC+B/L+CTP, 800(RGB)×1280 Resolution, 16.7M Colors, Transmissive a-Si TFT-LCD, IPS (Free), MIPI Interface, 2P16S Backlight (320mA), -20°C to +70°C Operation, Rev. V2.

1. Executive Summary & Product Positioning

The LSC101I35-MP-V2 is a 10.1-inch transmissive type a-Si TFT-LCD (amorphous silicon thin film transistor liquid crystal display) module developed by 立信(万安)智显科技有限公司 (Lesson Smart Display Technology Co., Ltd). The panel size is 10.1 inch and the resolution is 800(RGB)*1280, the panel can display up to 16.7M colors. This module is the Revision V2 of the product, featuring a capacitive touch panel (CTP).

Product Positioning: This module features a 10.1-inch IPS (In-Plane Switching) panel, offering superior viewing angles (IPS) and high color performance (16.7M colors). With a standard MIPI interface, it is well-suited for a wide range of applications such as industrial HMI, medical equipment, and other embedded display systems requiring a reliable and high-resolution display with touch functionality.

2. Detailed Product Overview & Architecture

The module's architecture is designed for robust performance and easy integration. The primary components include:

  • TFT-LCD Panel: 10.1-inch diagonal, a-Si TFT active matrix, transmissive, IPS mode. Resolution is 800(RGB) × 1280 pixels. The active area is 135.36 (H) × 216.58 (V) mm.
  • Driver Circuit: The module integrates a driver IC (JD9365DA-H3), communicating via an MIPI Interface.
  • Backlight Unit (B/L): A white LED backlight with LEDs configured in a 16 Parallel 2 Series (16P2S) arrangement. The typical driving condition is IF=320mA, Vf=11.2~13.6V.
  • Mechanical Construction: COG (Chip-on-Glass) + FPC + B/L + CTP (Capacitive Touch Panel). The module outer dimensions are 166 × 260.4 × 4.31 mm.
  • Interface: The module communicates via a 40-pin FPC connector. The display interface is MIPI (4 Data Lane).
  • Display Mode: Active matrix TFT, Transmissive type, IPS (Free).
  • Viewing Direction (Grayscale Inversion): Free (IPS).
  • RoHS: RoHS compliance is stated.

3. Exhaustive Technical Specifications

3.1 General & Mechanical Specifications

Item Specification
Display Size (Diagonal) 10.1 inches
Resolution (Dots) 800(RGB) × 1280
Display Technology Active Matrix TFT, Transmissive, a-Si, IPS (Free)
Module Construction COG+FPC+B/L+CTP
Color Depth 16.7M Colors
Display Technology Transmissive, IPS
Input Data Interface MIPI (4 Data Lanes)
Driver IC JD9365DA-H3
Module Size (H×V×D) 166 × 260.4 × 4.31 mm
Active Area (AA, H×V) 135.36 × 216.58 mm
Pixel Arrangement RGB Dot-matrix (800(RGB)×1280)
Display Mode Active matrix TFT, Transmissive type
Backlight Type White LED, 16P2S (16 parallel, 2 series)
Luminance (IF=320mA) 700 cd/m²
Operating Temperature -20°C to +70°C
Storage Temperature -30°C to +80°C

3.2 Electrical Characteristics

3.2.1 Backlight LED Characteristics

The backlight driving condition is IF=320mA, Vf=11.2~13.6V for a 16P2S LED configuration.

Parameter Symbol Min Typ Max Unit
Forward Voltage Vf 11.2 -- 13.6 V
Forward Current (Total) IF -- 320 -- mA

3.3 Interface Pin Assignment (40-Pin FPC)

The module communicates via a 40-pin FPC connector. The interface is MIPI.

PIN NO. Symbol I/O Description
1, 4, 6, 23, 24, 26, 27, 28, 29 NC -- No Connection
2 VDD P Power supply
3 IOVCC P Power supply
5 RESET I Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied
7, 10, 13, 16, 19, 22, 25, 30, 38 GND P Ground
8, 9 D0N, D0P I/O MIPI Data lane 0 differential signals
11, 12 D1N, D1P I MIPI Data lane 1 differential signals
14, 15 CLKN, CLKP I MIPI Clock differential signals
17, 18 D2N, D2P I MIPI Data lane 2 differential signals
20, 21 D3N, D3P I MIPI Data lane 3 differential signals
31, 32 LED- P Power for LED backlight cathode
33 TP_VDD2.8V P Power supply (for Touch Panel)
34 TP_INT1.8V I TP Interrupt signal
35 TP_SCL1.8v I SCL pin for TP
36 TP_SDA1.8V I/O TP Serial data input/output bidirection pin
37 TP_RST1.8 I TP Reset signal pin
39, 40 LED+ P Power for LED backlight anode

3.4 Electro-Optical Characteristics

Condition: Ta=25°C, viewing angle at center point, θx=θy=0.

Item Symbol Condition Min. Typ. Max. Unit
Response time Tr + Tf θx = θy =0 --- 25 35 ms
Contrast Ratio CR θx = θy =0 800 1000 --- ---
Transmittance T% θx = θy =0 4.65 5.41 --- %
Color Chromaticity (White) Wx, Wy θx = θy =0 --- 0.302, 0.329 --- CIE1931
Viewing angle (all directions) θT, θB, θL, θR CR>10 --- 80 --- Deg.
Luminance (IF=320mA) L --- --- 700 --- cd/m²

3.5 Timing Characteristics

3.5.1 MIPI DSI Clock Lane Timing

Key timing parameters for the MIPI DSI clock lane.

Parameter Description Min Max Unit
$T_{CLK-POST}$ Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. 60 + 52*UI - ns
$T_{CLK-PRE}$ Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. 8*UI - ns
$T_{CLK-PREPARE}$ Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. 38 95 ns
$T_{CLK-PREPARE}$ + $T_{CLK-ZERO}$ $T_{CLK-PREPARE}$ + time that the transmitter drives the HS-0 state prior to starting the Clock. 300 - ns
$T_{CLK-TERM-EN}$ Time for the Clock Lane receiver to enable the HS line termination. - 38 ns

3.5.2 Vertical & Horizontal Timing (MIPI)

Resolution=800x1280, TA=25°C, IOVCC=1.8V, VCIP=2.8V, VCI=2.8V.

Item Symbol Min. Typ. Max. Unit
Vertical low pulse width VS 2 4 200 Line
Vertical front porch VFP 4 20 200 Line
Vertical back porch VBP 2 10 200 Line
Vertical blanking period VBK 8 34 250 Line
Vertical active area VDISP - 1280 - Line
Vertical Refresh rate VRR - 60 - Hz

Horizontal Timing at Resolution=800x1280, TA=25°C, IOVCC=1.8V, VCIP=VC1=VCCH=2.8V.

Item Symbol Min. Typ. Max. Unit
HS low pulse width HS 6 18 78 DCK
Horizontal back porch HBP 5 18 78 DCK
Horizontal front porch HFP 5 18 78 DCK
Horizontal blanking period HBLK 16 54 (Note1) 88 DCK
Horizontal active area HDISP - 800 - DCK
Pixel Clock PCLK 63.06 (Note2) 67.33 (Note2) 81.51 (Note2) MHz

Note 1: HS+HBP > 0.5us.
Note 2: Pixel Clock = (HBLK+HDISP) * (VBK+VDISP) * Frame rate, Frame rate=60Hz.

3.6 Version Records (Revision V2 Change)

According to the Records of Version (Section 9), Revision V2 (2026-03-03) changed the following:

  • Functional sheet changed to 0.4mm.
  • Front hole moved up by 0.3mm.

3.7 Design Notes from Documentation

  • B/L Driver: The backlight driving condition is IF=320mA, Vf=11.2~13.6V for a 16P2S LED configuration.
  • Mechanical: Tolerance of segments to edge of glass: ±0.2mm.
  • Housing: It is recommended that the housing visual area be at least 0.3mm smaller than the VA (Viewing Area) on each side. The housing foam window should be at least 0.6mm larger than the VA on each side. TP edge should not contact metal conductors to avoid ESD or short circuit risks.
  • CTP Supply Voltage: The Capacitive Touch Panel (CTP) requires a 2.8V power supply for VDD and a 1.8V supply for the I2C interface logic (INT, SCL, SDA, RST).
  • Interface: The display uses a 4-lane MIPI DSI interface. The touch panel uses an I2C interface.
  • RoHS: RoHS compliance is expected.

4. Application Guidelines & Critical Notes

  • Power Supply: The module requires a 2.8V power supply for VDD and 1.8V for IOVCC (as per pin definition and timing conditions). The CTP requires separate 2.8V (TP_VDD) and 1.8V logic supplies. Ensure the power supply ripple is minimized.
  • Interface: This module uses a standard MIPI DSI (4-lane) protocol for the display and an I2C protocol for the touch panel. The host processor must be configured for these protocols.
  • Backlight Driver (External): An external constant current driver is required to supply the backlight via the LED+ and LED- pins. The required driving condition is 320mA total current at 11.2V to 13.6V forward voltage (for a 16P2S configuration).
  • Reset: A hardware reset pin (RESET, Pin 5) is provided. It must be reset after power is supplied to properly initialize the LSI.
  • Handling Precautions: Handle the module with care to avoid damage to the glass or FPC. Ground yourself to prevent electrostatic discharge (ESD).
  • Revision Note: This is the V2 revision of this module. Compared to the V1 version, the functional sheet thickness has been revised to 0.4mm, and the position of the front hole has been adjusted.

5. Conclusion & Design-In Support

The LSC101I35-MP-V2 from Lesson Smart Display Technology is a 10.1-inch IPS TFT-LCD module with an integrated Capacitive Touch Panel (CTP) and a MIPI interface. It is a high-resolution, wide-viewing-angle display solution suitable for a wide variety of industrial and consumer embedded display applications.

For successful design-in, engineers should:

  • Obtain and review the complete, official Product Specification (Revision 1.0) for the full mechanical drawing and the driver IC (JD9365DA-H3) and touch controller datasheet for detailed initialization and timing parameters.
  • Design a clean 2.8V/1.8V power supply for the LCD and a separate 2.8V/1.8V supply for the CTP. Design a backlight constant current driver circuit capable of delivering 320mA at 11.2V to 13.6V.
  • Configure the host processor's MIPI DSI (4-lane) and I2C interfaces to match the timing specifications detailed in the datasheets.
  • Contact the manufacturer for evaluation modules, sample requests, and further technical support during the design-in phase.

This module is designed to provide a reliable and vibrant display solution with integrated touch for a wide array of applications.

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Eddie Chen
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