LSL0395I13L-MP-V2 | 3.95 inch TFT-LCD | 720x720 | MIPI | IPS | COG+FPC+B/L+LENS
1. Executive Summary & Product Positioning
The LSL0395I13L-MP-V2 is a 3.95-inch transmissive type a-Si TFT-LCD (amorphous silicon thin film transistor liquid crystal display) module developed by 立信(万安)智显科技有限公司 (Lesson Smart Display Technology Co., Ltd). It is composed of a TFT-LCD panel, a driver circuit, and a backlight unit. The panel size is 3.95 inch and the resolution is 720(RGB)*720, the panel can display up to 16.7M colors.
Product Positioning: Designed for a wide range of compact, square-shaped display applications requiring a high-resolution IPS display with a standard MIPI interface, excellent image quality, and high brightness. With its 3.95-inch diagonal, high 720x720 resolution, wide viewing angle (IPS) and integrated LENS for a premium look, it is ideally suited for smart home controls, IoT devices, wearable hubs, and other portable or fixed human-machine interfaces.
2. Detailed Product Overview & Architecture
The module's architecture is designed for high performance and robust integration. The primary components include:
- TFT-LCD Panel: 3.95-inch diagonal, a-Si TFT active matrix, transmissive, IPS display mode. The resolution is 720(RGB) × 720 pixels with an active area of 71.93 × 71.93 mm.
- Driver IC: The module uses the FL7703NI driver IC, which supports a MIPI interface.
- Backlight Unit (B/L): A white LED edge-lit backlight unit. The backlight configuration is 6 strings 2 parallel. The driving condition is IF=40mA, Vf=18V(TYP).
- Mechanical Construction: COG (Chip-on-Glass) + FPC + B/L + LENS (Cover Lens). The module outline dimensions are 78.98 (H) × 78.98 (V) mm. The module includes a LENS for a fully laminated appearance.
- Interface: The module communicates via a 32-pin (or similar) connector. The main display interface is MIPI (Mobile Industry Processor Interface).
3. Exhaustive Technical Specifications
3.1 General & Mechanical Specifications
| Item | Specification |
| Display Size (Diagonal) | 3.95 inches |
| Resolution (Dots) | 720(RGB) × 720 |
| Display Technology | Active matrix TFT, Transmissive, a-Si |
| Display Format | Graphic 720(RGB)×720 Dot-matrix |
| Module Construction | COG+FPC+B/L+LENS |
| Color Depth | 16.7M Colors |
| Viewing Direction (Grayscale Inversion) | Free (IPS) |
| Input Data Interface | MIPI |
| Driver IC | FL7703NI |
| Number of Dots | 720(RGB) × 720 pixels |
| Active Area (H×V) | 71.93 × 71.93 mm |
| Module Size (H×V×D) | 77.02 × 83.88 × 2.97 mm (Note: from mechanical drawing) |
| Operating Temperature | -20°C to +70°C |
| Storage Temperature | -30°C to +80°C |
3.2 Electrical Specifications
3.2.1 Absolute Maximum Ratings
| Parameter | Symbol | Min | Max | Unit |
|---|---|---|---|---|
| Supply Voltage (IO) | IOVCC | -0.3 | 5.5 | V |
| Operating Temperature | TOPR | -20 | 70 | °C |
| Storage Temperature | TSTR | -30 | 80 | °C |
3.2.2 DC Characteristics (Ta=25°C)
| Parameter | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| Supply Voltage (Positive) | VSP | 4.5 | 5.5 | 6.2 | V |
| Supply Voltage (Negative) | VSN | -6.2 | -5.5 | -4.5 | V |
| Supply Voltage (IO) | IOVCC | 1.65 | 1.8 | 3.3 | V |
| Input Voltage (Low Level) | VIL | 0 | -- | 0.3*IOVCC | V |
| Input Voltage (High Level) | VIH | 0.7*IOVCC | -- | IOVCC | V |
3.2.3 Backlight LED Characteristics
The backlight uses a 6 string 2 parallel White LED configuration. The driving condition is IF=40mA, Vf=18V(TYP).
3.3 Interface & Pin Map (32-Pin Connector)
The module uses a 32-pin connector (HIROSE: BK13C06-32DP/2-0.35V(800)). The pinout integrates the MIPI interface, power supply, and backlight signals.
| Pin No. | Symbol | I/O | Description |
|---|---|---|---|
| 1 | GND | P | Ground |
| 2 | D3N | I | MIPI DSI Data Lane 3 Negative |
| 3 | D3P | I | MIPI DSI Data Lane 3 Positive |
| 4 | GND | P | Ground |
| 5 | D2N | I | MIPI DSI Data Lane 2 Negative |
| 6 | D2P | I | MIPI DSI Data Lane 2 Positive |
| 7 | GND | P | Ground |
| 8 | CLKN | I | MIPI DSI Clock Lane Negative |
| 9 | CLKP | I | MIPI DSI Clock Lane Positive |
| 10 | GND | P | Ground |
| 11 | D1N | I | MIPI DSI Data Lane 1 Negative |
| 12 | D1P | I | MIPI DSI Data Lane 1 Positive |
| 13 | GND | P | Ground |
| 14 | D0N | I/O | MIPI DSI Data Lane 0 Negative (Bidirectional) |
| 15 | D0P | I/O | MIPI DSI Data Lane 0 Positive (Bidirectional) |
| 16 | GND | P | Ground |
| 17 | GND | P | Ground |
| 18 | VCOM | O | VCOM output (2.2uF Capacitance) |
| 19 | GND | P | Ground |
| 20 | VDDD | O | NC (Not Connected) |
| 21 | VSN | P | Negative Power Supply (-5.5V Typical) |
| 22 | VSP | P | Positive Power Supply (+5.5V Typical) |
| 23 | VGH | O | Gate High Voltage (1uF Capacitance) |
| 24 | VGL | O | Gate Low Voltage (1uF Capacitance) |
| 25 | TE | O | Tearing Effect Output (Synchronization Signal) |
| 26 | RESX | I | System Reset Pin (Low Active) |
3.4 Optical Specifications
Optical characteristics are measured at θx = θy = 0°, Ta=25°C.
| Item | Symbol | Condition | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Response Time (Tr+Tf) | Tr+Tf | θx = θy = 0° | -- | 30 | 40 | ms |
| Contrast Ratio | CR | θx = θy = 0° | 900 | 1200 | -- | -- |
| Transmittance | T% | θx = θy = 0° | 4.2 | 4.8 | -- | % |
| Color Chromaticity (White) - CIE1931 | Wx, Wy | θx = θy = 0° | -- | 0.294, 0.323 | -- | -- |
| Viewing Angle (All Directions) | θT, θB, θL, θR | CR > 10 | 80 | 85 | -- | Deg. |
| LCM Luminance (IF=40mA) | L | IF = 40mA | 400 | 500 | -- | cd/m² |
3.5 Interface Timing Characteristics (MIPI DSI)
The module supports MIPI DSI interface with the following key parameters (Test Condition: VSSA=0V, IOVCC=1.65V to 3.3V, VCI=2.5V to 3.3V, TA = -30 to 70°C). The module supports up to 4 data lanes.
3.5.1 High Speed (HS) Mode Characteristics
| Signal | Item | Symbol | Min | Max | Unit |
|---|---|---|---|---|---|
| DSI_CP/DSI_CN | Double UI instantaneous | 2xUINST | 3.30 (4 LANE) | 25 | ns |
| DSI_CP/DSI_CN | UI instantaneous | UINSTA UINSTB | 1.67 (4 LANE) | 12.5 | ns |
| DP/DN | Data to clock setup time | TDS | 0.15xUI | -- | ps |
| DP/DN | Data to clock hold time | TDH | 0.15xUI | -- | ps |
| DSI_CP/DSI_CN | Differential rise/fall time (Clock) | TDRTCLK/TDFTCLK | 150 | 0.3UI | ps |
| DP/DN | Differential rise/fall time (Data) | TDRTDATA/TDFTDATA | 150 | 0.3UI | ps |
3.5.2 Clock Lane Timing
| Signal | Item | Symbol | Min | Max | Unit |
|---|---|---|---|---|---|
| DSI_CP/DSI_CN | Time to drive LP-00 to prepare for HS | TCLK-PREPARE | 38 | 95 | ns |
| DSI_CP/DSI_CN | Min lead HS-0 drive period before starting Clock | TCLK-PREPARE + TCLK-ZERO | 300 | -- | ns |
| DSI_CP/DSI_CN | Time to drive LP-11 after HS burst | THS-EXIT | 100 | -- | ns |
| DSI_CP/DSI_CN | Time to drive HS differential state after last payload clock bit | TCLK-TRAIL | 60 | -- | ns |
| DSI_CP/DSI_CN | Time that the MCU shall continue sending HS clock after the last associated Data Lane has transitioned to LP | TCLK-POST | 60+52xUI | -- | ns |
3.5.3 Reset Timing
| Parameter | Symbol | Min | Max | Unit |
|---|---|---|---|---|
| Reset low pulse width | tRESW | 10 | -- | μs |
| Reset complete time (SLPIN mode) | tREST | -- | 15 | ms |
| Reset complete time (SLPOUT mode) | tREST | -- | 120 | ms |
Note: Spike rejection applies. A reset pulse shorter than 5μs is rejected. It is necessary to wait 15ms after releasing RESX before sending commands. Sleep Out command cannot be sent for 120ms.
4. Application Guidelines & Critical Notes
When integrating the LSL0395I13L-MP-V2 module, engineers must adhere to the specific guidelines outlined in the specification to ensure optimal performance and reliability.
- Power Supply (Multiple Rails): The module requires several supply rails: IOVCC (1.8V or 3.3V) for the I/O interface, VSP (Positive ~5.5V) and VSN (Negative ~-5.5V) for the panel drive. The I/O voltage level must match the host's logic level.
- MIPI Interface (4-Lane + Clock): This is a full 4-lane MIPI DSI interface. The host processor must have a compatible MIPI DSI transmitter with 4 data lanes and a clock lane. The PCB layout for the differential pairs must be carefully designed for controlled impedance (100-ohm differential) and matched trace lengths.
- Backlight Driver (External): The module provides separate LED Anode (LEDA) and Cathode (LEDK) pins. The backlight configuration is 6 strings 2 parallel, requiring a total drive current of 40mA at a forward voltage of 18V. An external constant current driver is required.
- Mechanical Integration: The module includes a LENS (cover glass). The specification notes critical mechanical guidelines such as: The enclosure viewing area should be 0.3mm smaller than the LENS VA per side, and the foam opening should be 0.6mm larger than the VA MDS per side.
- Handling Precautions: The module uses a glass LCD panel and LENS. Handle with care to avoid breakage. The TP edge cannot contact metal conductors. Silver paste points are present for ESD protection.
- RoHS Compliance: This module is designed to comply with RoHS directives.
- Reset Timing: The reset pulse must be at least 10μs wide. After releasing the reset, a waiting period of 15ms is required before sending any commands. If the reset is applied during Sleep Out mode, the display will blank for up to 120ms.
5. Conclusion & Design-In Support
The LSL0395I13L-MP-V2 from Lesson Smart Display Technology is a feature-rich, high-resolution 3.95-inch TFT-LCD module. Its combination of a square high resolution (720x720), full 4-lane MIPI interface, wide viewing angle (IPS), integrated LENS, and high brightness (500 cd/m² Typ) makes it an excellent choice for a wide variety of premium applications.
For design-in support, it is strongly recommended to:
- Obtain and review the full Product Specification (Revision 1.0) for the complete set of electrical parameters, interface timing diagrams, mechanical drawings (including the outline dimension drawing), and the FL7703NI driver IC datasheet.
- Design the power supply to provide IOVCC, VSP, and VSN rails. Design a constant current backlight driver (40mA at ~18V).
- Develop firmware using the standard MIPI DSI protocol for the FL7703NI driver IC.
- Contact the manufacturer for evaluation kits, sample requests, and technical support during the design-in phase.
This module is engineered to deliver reliable, vibrant, and premium-quality display performance for modern electronic products.
