Product Subtitle / Keywords:
2.4 Inch Display, QVGA 240x320 Resolution, Transmissive a-Si TN TFT, 3-Wire/4-Wire Serial & 8-Bit/16-Bit Parallel Interfaces, COG+FPC+B/L, 262K Colors, ST7789T3 Driver, 39-pin FPC, -20°C~70°C Operating Temperature
1. Executive Summary & Product Positioning
The LS024T04-M-V2, developed by LESSON (Wan'an) Zhixian Technology Co., Ltd. (立信(万安)智显科技有限公司), is a 2.4-inch transmissive amorphous Silicon TFT-LCD module.
This product specification book (Revision 1.0, Model No: LS024T04-M-V2, Module Type: COG+FPC+B/L) serves as the definitive technical document, defining its structural composition (COG+FPC+B/L), mechanical dimensions, absolute maximum ratings, detailed electrical characteristics, multi-interface support (3-wire serial, 4-wire serial, 8-bit parallel, 16-bit parallel) pinout and timing, and comprehensive electro-optical performance. It delivers a QVGA resolution of 240(RGB)×320 with 262K-color display capability, driven by the ST7789T3 controller.
The document provides the core parameters necessary for system integration into embedded display applications. The unequivocal recommendation for engineers is to strictly adhere to the electrical specifications, interface timing, and mechanical tolerances described herein to ensure reliable performance and compatibility.
2. Detailed Product Overview & Architecture
- Core Technology: Transmissive-type a-Si TFT-LCD (amorphous silicon thin film transistor liquid crystal display).
- Display Mode: Active matrix TFT, Transmissive type.
- Display Characteristics: Capable of displaying up to 262 thousand colors.
- Module Construction: COG (Chip-On-Glass) + FPC (Flexible Printed Circuit) + B/L (Backlight Unit). Composed of a TFT-LCD panel, a driver circuit, and a backlight unit.
- Input Data: Configurable via IM[1:0] pins to support:
- 3-wire Serial Interface (9-bit)
- 4-wire Serial Interface (8-bit)
- 8-bit Parallel Interface (8080 MCU)
- 16-bit Parallel Interface (8080 MCU)
- Viewing Direction (Grayscale Inversion): TN (Twisted Nematic).
- Drive IC: ST7789T3.
- Backlight: 4 Chip-White LEDs in Parallel.
- Environmental Compliance: ROHS Compliant.
- Approval Status: Approved Product Specification only (as per signature block).
3. Exhaustive Technical Specifications
3.1 Mechanical & Physical Specifications
| Item | Specification | Unit |
|---|---|---|
| Module size (H×V×D) | 42.72 × 60.26 × 2.15 | mm |
| Active area (H×V) | 36.72 × 48.96 | mm |
| Number of dots / Resolution | 240(RGB) × 320 | pixel |
| Panel Size (Diagonal) | 2.4 | inch |
Critical Mechanical Design Notes (from document):
- Display Type: Main LCD: Transmissive, TN.
- Operating Temperature: -10°C ~ +60°C (Note: The DC characteristics table shows -20°C~70°C; the outline drawing notes show -10°C~60°C. The more restrictive value of -10°C to +60°C should be used for design).
- Storage Temperature: -20°C ~ +70°C.
- Main LCD Driver: ST7789T3.
- Backlight: 4 Chip-White LED Parallel.
- ROHS Compliance: Yes.
- Bezel Opening Design: It is recommended that the housing's visible area be at least 0.3mm smaller per side than the module's active area (VAMds).
- Foam Gasket Cutout Design: The cutout in the chassis foam gasket should be at least 0.6mm larger per side than the module's viewing area (VAMds).
- TP/Conductor Isolation: The Touch Panel (TP) edges must not come into contact with any metal conductors.
- Glass Segment to Edge Tolerance: ±0.2 mm.
3.2 Electrical & Interface Specifications
3.2.1 Absolute Maximum Ratings
| Item | Symbol | Min | Max | Unit | Remark |
|---|---|---|---|---|---|
| Supply voltage | VCC | -0.3 | 4.6 | V | Note1, Note2 |
| I/O Supply voltage | IOVCC | -0.3 | 4.6 | V | Note1, Note2 |
| Operating temperature | TOPR | -20 | 70 | °C | Note1, Note2 |
| Storage temperature | TSTR | -30 | 80 | °C | Note1, Note2 |
Notes (interpreted):
- Note1/Note2: Stress beyond these ratings may cause permanent damage; functional operation is not implied under these conditions.
3.2.2 Electrical Characteristics (DC – Recommended Operating Conditions)
| Item | Item | Symbol | Min | Typ | Max | Unit | Remark |
|---|---|---|---|---|---|---|---|
| Supply voltage | Supply voltage | VCC | 2.4 | 2.75 | 3.3 | V | Note1 |
| I/O Supply voltage | I/O Supply voltage | IOVCC | 1.65 | 1.8 | 3.3 | V | Note1 |
| Input Voltage (Low level) | Input Voltage (Low level) | VIL | 0 | — | 0.3 * IOVCC | V | Note1 |
| Input Voltage (High level) | Input Voltage (High level) | VIH | 0.7 * IOVCC | — | IOVCC | V | Note1 |
3.2.3 Pin Description (39-pin FPC)
| PIN NO. | Symbol | I/O | Description |
|---|---|---|---|
| 1-4 | NC | — | No Connection |
| 5 | GND | P | Ground |
| 6 | IOVCC | P | I/O power supply for LCM (2.8V-3.3V) |
| 7 | VCI | P | Main power supply for LCM (2.8V-3.3V) |
| 8 | FMARK | O | Tearing effect output pin. If not used, open this pin. |
| 9 | CS/SPI_CS | I | Chip select pin (Low enable) |
| 10 | RS/SPI_SCL/SCK | I | Data/Command select in parallel; Serial clock in 3-wire/4-wire serial mode |
| 11 | WR/A0(4-line) | I | Write signal (parallel) or D/CX select (4-line serial). Fix to IOVCC when unused. |
| 12 | RD | I | Read signal (parallel). Fix to IOVCC when unused. |
| 13 | SPI_SDI/SDA | I | Serial data input. Fix to IOVCC or GND when unused. |
| 14 | SPI_SDO | O | Serial data output. Open when unused. |
| 15 | RESET | I | LCM Reset pin. Active low. |
| 16 | GND | P | Ground |
| 17-24 | DB0-DB7 | I/O | Lower 8-bit data bus. Fix to GND when unused. |
| 25-32 | DB8-DB15 | I/O | Upper 8-bit data bus. Fix to GND when unused. |
| 33 | A | P | Anode of Backlight (3.0V-3.4V, Typical: 3.2V) |
| 34-36 | K | P | Cathode of Backlight |
| 37 | GND | P | Ground |
| 38-39 | IM1, IM0 | I | Interface Mode selection pins |
Interface Mode Selection (IM1, IM0 Pins):
| IM1 | IM0 | Data Pins | MPU Interface Mode |
|---|---|---|---|
| 0 | 0 | DB[0:15] | 80-16bit parallel |
| 1 | 0 | DB[0:7] | 80-8bit parallel |
| 0 | 1 | SDA_IN, SDO_OUT | 3-line 9-bit serial |
| 1 | 1 | SDA_IN, SDO_OUT | 4-line 8-bit serial |
Interface Summary:
- This module offers exceptional interface flexibility: 4 different interface modes are selectable via the IM[1:0] pins.
- In parallel modes, a full 16-bit or 8-bit data bus is available.
- In serial modes, SDA is used for data input and SDO for data output.
- The backlight uses 3 dedicated cathode pins (Pins 34-36) in parallel.
3.2.4 Interface Timing Characteristics (Parallel - 8080 MCU Interface)
Conditions: VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25°C.
| Signal | Symbol | Parameter | MIN | MAX | Unit | Description |
|---|---|---|---|---|---|---|
| D/CX | T_AST | Address setup time | 0 | — | ns | |
| D/CX | T_AHT | Address hold time (Write/Read) | 10 | — | ns | |
| CSX | T_CHW | Chip select "H" pulse width | 0 | — | ns | |
| CSX | T_CS | Chip select setup time (Write) | 15 | — | ns | |
| CSX | T_RCS | Chip select setup time (Read ID) | 45 | — | ns | |
| CSX | T_RCSFM | Chip select setup time (Read FM) | 355 | — | ns | |
| CSX | T_CSF | Chip select wait time (Write/Read) | 10 | — | ns | |
| CSX | T_CSH | Chip select hold time | 10 | — | ns | |
| WRX | T_WC | Write cycle | 66 | — | ns | |
| WRX | T_WRH | Control pulse "H" duration | 15 | — | ns | |
| WRX | T_WRL | Control pulse "L" duration | 15 | — | ns | |
| RDX (ID) | T_RC | Read cycle (ID) | 160 | — | ns | When read ID data |
| RDX (ID) | T_RDH | Control pulse "H" duration (ID) | 90 | — | ns | When read ID data |
| RDX (ID) | T_RDL | Control pulse "L" duration (ID) | 45 | — | ns | When read ID data |
| RDX (FM) | T_RCFM | Read cycle (FM) | 450 | — | ns | When read from frame memory |
| RDX (FM) | T_RDHFM | Control pulse "H" duration (FM) | 90 | — | ns | When read from frame memory |
| RDX (FM) | T_RDLFM | Control pulse "L" duration (FM) | 355 | — | ns | When read from frame memory |
| D[17:0] | T_DST | Data setup time | 10 | — | ns | For CL=30pF |
| D[17:0] | T_DHT | Data hold time | 10 | — | ns | |
| — | T_RAT | Read access time (ID) | — | 40 | ns | |
| — | T_RATFM | Read access time (FM) | — | 340 | ns | |
| — | T_DOH | Output disable time | 20 | 80 | ns |
Key Timing for Parallel Interface:
- Write Cycle: Minimum 66ns (equivalent to 15.15 MHz).
- Read Cycle (ID): Minimum 160ns.
- Read Cycle (FM - Frame Memory): Minimum 450ns.
3.2.5 Serial Interface Timing Characteristics (4-line Serial)
Conditions: VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25°C.
A. Write Operation (Serial):
| Signal | Symbol | Parameter | MIN | MAX | Unit | Description |
|---|---|---|---|---|---|---|
| CSX | T_CSS | Chip select setup time (write) | 15 | — | ns | |
| CSX | T_CSH | Chip select hold time (write) | 15 | — | ns | |
| CSX | T_CHW | Chip select "H" pulse width | 40 | — | ns | |
| SCL | T_SCYCW | Serial clock cycle (Write) | 16 | — | ns | For write command & data RAM |
| SCL | T_SHW | SCL "H" pulse width (Write) | 7 | — | ns | |
| SCL | T_SLW | SCL "L" pulse width (Write) | 7 | — | ns | |
| SDA (DIN) | T_SDS | Data setup time | 7 | — | ns | |
| SDA (DIN) | T_SDH | Data hold time | 7 | — | ns |
B. Read Operation (Serial):
| Signal | Symbol | Parameter | MIN | MAX | Unit | Description |
|---|---|---|---|---|---|---|
| CSX | T_CSS | Chip select setup time (read) | 60 | — | ns | |
| CSX | T_SCC | Chip select hold time (read) | 65 | — | ns | |
| SCL | T_SCYCR | Serial clock cycle (Read) | 150 | — | ns | For read command & data RAM |
| SCL | T_SHR | SCL "H" pulse width (Read) | 60 | — | ns | |
| SCL | T_SLR | SCL "L" pulse width (Read) | 60 | — | ns | |
| D/CX | T_DCS | D/CX setup time | 10 | — | ns | |
| D/CX | T_DCH | D/CX hold time | 10 | — | ns | |
| DOUT | T_ACC | Access time | 10 | 50 | ns | For CL=30pF(max)/8pF(min) |
| DOUT | T_OH | Output disable time | 15 | 50 | ns | For CL=30pF(max)/8pF(min) |
Key Observation for Serial Interface:
- Very fast 16ns write cycle (62.5 MHz) for serial writes.
- Significantly slower 150ns read cycle (6.67 MHz) for serial reads.
3.2.6 Backlight Unit
| Item | Specification | Unit |
|---|---|---|
| Configuration | 4 Chip-White LEDs in Parallel | — |
| Anode Pin | Pin 33 (A) | — |
| Cathode Pins | Pins 34-36 (K) | — |
| Drive Condition | IF=80mA, VF=2.8~3.2V (Typ.) | — |
Note: The backlight uses 4 parallel LEDs driven via a single anode pin and 3 cathode pins. A constant-current LED driver set to 80 mA with a forward voltage range of 2.8V to 3.2V is required.
3.3 Optical & Electro-Optical Characteristics
(Note: The complete optical characteristics table (Section 8 - Electro-Optical Characteristics) is referenced in the document's table of contents but the specific numerical values are not provided in the given document excerpt. The full specification document would contain this information.)
4. Application Guidelines & Critical Notes
Intended Use
- Embedded systems requiring interface flexibility
- Industrial controls and HMIs
- Consumer electronics
- Portable instruments
- Applications requiring compatibility with both high-speed parallel and simple serial interfaces
Critical Design Considerations
-
Interface Selection – CRITICAL:
- Configure the IM1 and IM0 pins (Pins 38-39) according to the desired interface mode before power-up. These pins determine the function of several other pins.
- For 16-bit parallel mode: Use all DB[0:15] pins. This offers the fastest data transfer.
- For 8-bit parallel mode: Use only DB[0:7] pins. DB[8:15] must be tied to GND.
- For serial mode: Pins WR, RD, and DB[0:15] must be properly terminated (tied to IOVCC or GND as specified in the pin description) to avoid floating inputs.
-
Power Supply:
- Provide stable VCC (2.4-3.3V, 2.75V typical) for the core logic.
- Provide stable IOVCC (1.65-3.3V, 1.8V typical) for the I/O interface.
- Both power pins are rated for the same absolute maximum of 4.6V.
-
Backlight Drive:
- The backlight uses 4 LEDs in parallel with 3 cathode pins (Pins 34-36). Ensure all 3 cathode pins are properly connected to the current sink.
- Design a constant-current LED driver set to 80 mA at approximately 3.0V forward voltage.
- The anode voltage range is 3.0V-3.4V (Typical 3.2V).
-
Unused Pin Termination:
- Serial mode: DB[0:7] and DB[8:15] must be tied to GND. WR and RD pins must be tied to IOVCC.
- Parallel mode: SPI_SDI/SDA must be tied to IOVCC or GND. SPI_SDO must be left open. FMARK must be left open.
- Proper termination of unused pins is essential to prevent noise-induced issues and excess power consumption.
-
FMARK Pin (Pin 8):
- This is the Tearing Effect output pin. When activated by software command, it can be used to synchronize the MCU to frame writing. If not used, leave it open.
-
Reset Circuit:
- The RESET pin (Pin 15) must be driven low for a sufficient period (typically >10 µs) during power-up.
-
Parallel Interface Timing:
- Write cycle: 66ns minimum (15.15 MHz) – ensure your host MCU's external memory interface can meet this timing.
- Read from frame memory: 450ns minimum – significantly slower, which may impact performance if used extensively.
-
Serial Interface Timing:
- Write cycle: 16ns minimum (62.5 MHz) – a very fast SPI interface.
- Read cycle: 150ns minimum (6.67 MHz) – much slower than writes.
-
Temperature Limits:
- Note the discrepancy between the outline drawing (-10°C to +60°C) and the absolute maximum ratings table (-20°C to +70°C). For reliable operation, design for -10°C to +60°C.
-
Mechanical Integration:
- Bezel Opening: Design the housing window 0.3mm smaller per side than the viewing area.
- Foam Gasket Cutout: Design the cutout 0.6mm larger per side than the viewing area.
- The module outline is identical to many other 2.4-inch 240x320 modules, simplifying mechanical reuse.
Handling & Compliance
- The module is ROHS compliant.
- Observe standard ESD precautions during handling and assembly.
- The module contains fragile glass and a 39-pin FPC – handle with care.
- Avoid bending the FPC sharply, especially near the connector interface.
5. Conclusion & Design-In Support
The LS024T04-M-V2 specification details a highly versatile 2.4-inch QVGA TN display module with the ST7789T3 driver and exceptional interface flexibility.
Key Strengths:
-
Multi-Interface Support: The ability to select between 3-wire serial, 4-wire serial, 8-bit parallel, and 16-bit parallel interfaces makes this module compatible with a wide range of microcontrollers, from low-pin-count MCUs to high-performance processors with external memory interfaces.
-
Fast Write Speeds: Whether using the 66ns parallel write cycle or the 16ns serial write cycle, this module supports high-speed screen updates.
-
Detailed Timing Specifications: The document provides complete timing parameters for both parallel and serial interfaces, including write/read cycles, setup/hold times, and chip select timings.
-
Standard Form Factor: The 42.72 × 60.26 mm module size is a common standard for 2.4-inch displays, allowing for mechanical compatibility with existing designs.
-
FMARK (Tearing Effect) Support: The dedicated FMARK pin enables synchronization of graphics updates with the display's refresh cycle, preventing screen tearing artifacts.
-
Full 16-bit Data Bus: In 16-bit parallel mode, the module can transfer 16 bits per write cycle for maximum performance.
Main Design Focus:
- Interface Configuration: The most critical design task is correctly setting the IM1 and IM0 pins to select the desired interface mode and properly terminating all unused pins.
- Driver Development: Software engineers must initialize the ST7789T3 driver IC according to the selected interface mode, configure the correct operating mode, and implement the appropriate display buffer management strategy.
- Power Management: Provide stable VCC (2.75V) and IOVCC (1.8V) power, and a constant-current backlight driver set to 80 mA.
- Mechanical Integration: Follow the bezel opening and foam cutout guidelines to ensure optimal display quality.
This module is an excellent, universally compatible solution for applications that may need to switch between different microcontrollers or interface types, or for designs where the same PCB can support multiple display interface options through hardware configuration.
