Product Subtitle / Keywords:
5.93 Inch Display, HD+ 720x1440 Resolution, Transmissive a-Si TFT IPS, MIPI DSI Interface, COG+FPC+B/L, 16.7M Colors, 300 cd/m² Brightness, Free Viewing Direction (IPS), ILI9881C-05 Driver, -20°C~70°C Operating Temperature

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1. Executive Summary & Product Positioning

The LSI0593HD-MP027, developed by LESSON (Wan'an) Zhixian Technology Co., Ltd. (立信(万安)智显科技有限公司), is a 5.93-inch transmissive amorphous Silicon TFT-LCD module featuring IPS (In-Plane Switching) technology.

 

This product specification book (Revision 1.0, Module Type: COG+FPC+B/L) serves as the definitive technical document, defining its structural composition (COG+FPC+B/L), physical features, mechanical dimensions, absolute maximum ratings, detailed electrical characteristics, complete MIPI DSI (Display Serial Interface) pinout and timing, and comprehensive electro-optical performance. It delivers an HD+ resolution of 720(RGB)×1440 with 16.7M-color display capability, driven by the ILI9881C-05 controller.

The document provides the complete technical basis for system integration. The unequivocal recommendation for engineers is to strictly adhere to the electrical specifications, interface timing, mechanical tolerances, and environmental limits described herein to ensure reliable operation and optimal display quality.

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2. Detailed Product Overview & Architecture

• Core Technology: Transmissive-type a-Si TFT-LCD (amorphous silicon thin film transistor liquid crystal display).
• Display Format: Graphic 720(RGB)×1440 Dot-matrix.
• Display Characteristics: Capable of displaying up to 16.7 million colors.
• Module Construction: COG (Chip-On-Glass) + FPC (Flexible Printed Circuit) + B/L (Backlight Unit). Composed of a TFT-LCD panel, a driver circuit, and a backlight unit.
• Input Data: 4-line serial interface (MIPI DSI).
• Viewing Direction (Grayscale Inversion): Free (IPS) – excellent viewing angles from all directions.
• Drive IC: ILI9881C-05.
• Display Mode: 16.7M Color TFT, Transmissive, Normally Black Mode.
• Module Luminance (without CTP): 300 cd/m².

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3. Exhaustive Technical Specifications

3.1 Mechanical & Physical Specifications

Item	Specification	Unit
Panel Size (Diagonal)	5.93	inch
Resolution	720(RGB) × 1440	pixel

(Note: Specific module outline dimensions and active area are provided in the outline dimension drawing of the full specification document but are not fully detailed in the provided context excerpt.)

Critical Mechanical Design Notes (from document):

1. Display Type: TFT-LCD Module, Active matrix TFT, Transmissive type.
2. Operating Temperature: -20°C ~ +70°C.
3. Storage Temperature: -30°C ~ +80°C.
4. ROHS Compliance: Yes – all materials must comply with ROHS and halogen-free standards.
5. General Tolerance: ±0.20 mm.
6. Viewing Direction: ALL (IPS).
7. Backlight: IF=40mA Vf=24V→25.6V (from outline dimension notes). This indicates the backlight consists of multiple LEDs in series.

3.2 Electrical & Interface Specifications

3.2.1 Absolute Maximum Ratings

Item	Symbol	Min	Max	Unit	Remark
Supply voltage	VCC	-0.3	7.0	V	Note1, Note2
Supply voltage	IOVCC	-0.3	3.8	V	Note1, Note2
Operating temperature	TOPR	-20	70	°C	Note1, Note2
Storage temperature	TSTR	-30	80	°C	Note1, Note2

Critical Observation: The main supply voltage (VCC) has a maximum absolute rating of 7.0V, which is significantly higher than many typical LCD modules (usually 4.6V). The I/O supply voltage (IOVCC) has a maximum of 3.8V, which is standard.

Notes (interpreted):

• Note1/Note2: Stress beyond these ratings may cause permanent damage; functional operation is not implied under these conditions.

3.2.2 Electrical Characteristics (DC – Recommended Operating Conditions)

(Note: The specific DC characteristics table (Recommended Operating Conditions) is referenced in the document's table of contents under Section 6 - Electrical Characteristics, but the exact numerical values are not explicitly provided in the given context excerpt. The absolute maximum ratings above provide the safe operating boundaries.)

3.2.3 Pin Description (40-pin FPC)

PIN NO.	Symbol	I/O	Description
27	GND	P	Ground
28-29	LED-	P	LED cathode (Backlight)
30	GND	P	Ground
31	NC	—	No Connection
32-33	GND	P	Ground
34	NC	—	No Connection
35-36	LED+	P	LED anode (Backlight)
37	GND	P	Ground
38-39	VCC	P	Power voltage (Main Logic Supply)
40	NC	—	No Connection

(Note: The full pin description from the document includes a more complete table with MIPI DSI data and clock pins, ground pins, and power pins. The excerpt provided shows the last portion of the table. The complete interface includes MIPI DSI differential data pairs (D0P/N, D1P/N, D2P/N, D3P/N — likely 4 lanes) and a differential clock pair (CLKP/N) based on the MIPI timing section.)

3.2.4 MIPI DSI Timing Characteristics (ILI9881C-05)

A. High Speed Mode – Clock Channel Timing:

Signal	Symbol	Parameter	Min	Max	Unit
CLKP/N	2xUI_INST	Double UI instantaneous	Note 2	25	ns
CLKP/N	UI_INSTA, UI_INSTB (Note 1)	UI instantaneous Half	Note 2	12.5	ns

Notes:

1. UI = UI_INSTA = UI_INSTB.
2. The minimum value is defined by the limited clock channel speed table.

Limited Clock Channel Speed:

Data type	Two Lanes speed	Three Lanes speed	Four Lanes speed
Data Type = 00 1110 (0Eh), RGB 565, 16 UI per Pixel	566 Mbps	466 Mbps	366 Mbps
Data Type = 01 1110 (1Eh), RGB 666, 18 UI per Pixel	637 Mbps	525 Mbps	412 Mbps
Data Type = 10 1110 (2Eh), RGB 666 Loosely, 24 UI per Pixel	850 Mbps	750 Mbps	650 Mbps
Data Type = 11 1110 (3Eh), RGB 888, 24 UI per Pixel	850 Mbps	750 Mbps	650 Mbps

B. High Speed Mode – Rising and Falling Timings:

Parameter	Symbol	Condition	Min	Typ	Max	Unit
Differential Rise Time for Clock	t_DRCLK	CLKP/N	150 ps	—	0.3UI (Note)	—
Differential Rise Time for Data	t_DRDATA	DnP/N n=0 and 1	150 ps	—	0.3UI (Note)	—
Differential Fall Time for Clock	t_DFCLK	CLKP/N	150 ps	—	0.3UI (Note)	—
Differential Fall Time for Data	t_DFDATA	DnP/N n=0 and 1	150 ps	—	0.3UI (Note)	—

Note: The display module has to meet timing requirements, which are defined for the transmitter (MCU) on MIPI D-Phy standard.

C. Low Speed Mode – Bus Turn Around (BTA) Timings:

Signal	Symbol	Description	Time	Unit
DOP/N	T_TAGETD	Time to drive LP-00 by Display Module (ILI9881C-04)	5xT_LPXD	ns
DOP/N	T_TAGOD	Time to drive LP-00 after turnaround request – MCU	4xT_LPXD	ns

D. Data Lanes – Low Power Mode to High Speed Mode Timings:

Signal	Symbol	Description	Min	Max	Unit
DnP/N, n = 0 and 1	T_LPX	Length of any Low Power State Period	50	—	ns
DnP/N, n = 0 and 1	T_HS-PREPARE	Time to drive LP-00 to prepare for HS Transmission	40+4xUI	85+6xUI	ns
DnP/N, n = 0 and 1	T_HS-TERM-EN	Time to enable Data Lane Receiver line termination	—	35+4xUI	ns

E. Data Lanes – High Speed Mode to Low Power Mode Timings:

Signal	Symbol	Description	Min	Max	Unit
CLK/N	T_CLK-POST	Time the MCU shall continue sending HS clock after last associated Data Lanes has transitioned to LP mode	60+52xUI	—	ns
CLK/N	T_CLK-TRAIL	Time to drive HS differential state after last payload clock bit	60	—	ns
CLK/N	T_HS-EXIT	Time to drive LP-11 after HS burst	100	—	ns
CLK/N	T_CLK-PREPARE	Time to drive LP-00 to prepare for HS transmission	38	95	ns
CLK/N	T_CLK-TERM-EN	Time-out at Clock Lane to enable HS termination	—	38	ns
CLK/N	T_CLK-PREPARE + T_HS-ZERO	Minimum lead HS-0 drive period before starting Clock	300	—	ns
CLK/N	T_CLK-PRE	Time the HS clock shall be driven prior to any associated Data Lane beginning the transition from LP to HS mode	8xUI	—	ns

F. DSI Video Mode Timing (for 720x1440 resolution):

Parameters	Symbols	Min.	Typ.	Max.	Units
Vertical sync. active	VSA	2 (Note g)	—	—	Line
Vertical Back Porch	VBP	14 (Note g)	—	—	Line
Vertical Front Porch	VFP	8 (Note g)	—	—	Line
Active lines per frame	VACT	—	1280	—	Line
Horizontal sync. active	HSA	2	—	—	Pixel
Horizontal Porch period	HSA + HBP + HFP	1.6	—	—	us
Active pixels per line	HACT	—	720	—	Pixel
Bit rate	BR_bps	385	—	Note 5	Mbps/lane

Note g: The vertical timing parameters (VSA, VBP, VFP) are specified with a note indicating they have a minimum value, suggesting a specific constraint or dependency.

G. Reset Timing:

Signal	Symbol	Parameter	Min	Max	Unit
RESX	t_RW	Reset pulse duration	10	—	uS
RESX	t_RT	Reset cancel	—	5 (note 1.5)	mS
RESX	t_RT	Reset cancel	—	120 (note 1.6.7)	mS

Reset Description Table:

RESX Pulse	Action
Shorter than 5us	Reset Rejected
Longer than 10us	Reset
Between 5us and 10us	Reset starts

Critical Reset Notes:

1. The reset cancel also includes required time for loading ID bytes, VCOM setting and other settings from EEPROM to registers. This loading is done every time there is a H/W reset cancel time (t_RT) within 5 ms after a rising edge of RESX.
2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the Reset Description table.
3. During the Resetting period, the display will be blanked (The display enters the blanking sequence, which maximum time is 120 ms, when Reset Starts in the Sleep Out mode. The display remains the blank state in the Sleep In mode.) and then return to Default condition for Hardware Reset.

3.2.5 Backlight Unit

Item	Specification	Unit
LED Configuration	16 LEDs	—
Drive Condition	IF = 40 mA, VF = 24V → 25.6V	—
Anode Pins	LED+ (Pins 35-36)	—
Cathode Pins	LED- (Pins 28-29)	—

Critical Note: The backlight uses 16 LEDs arranged in a series configuration, resulting in a high forward voltage of 24V to 25.6V at a current of 40 mA. This is a high-voltage, low-current backlight configuration requiring a specialized LED driver.

3.3 Optical & Electro-Optical Characteristics (Ta=25°C)

Item	Item	Symbol	Condition	Min.	Typ.	Max.	Unit	Remark
Response time	Response time	Tr + Tf	θx = θy = 0	—	35	40	ms	Note 1
Contrast Ratio	Contrast Ratio	CR	θx = θy = 0	—	1000	—	—	Note 2
Transmittance	Transmittance	T%	θx = θy = 0	3.1	3.7	—	%
Color Chromaticity (CIE1931)	White	Wx	θx = θy = 0	—	0.294	—	—
Color Chromaticity (CIE1931)	White	Wy	θx = θy = 0	—	0.327	—	—
Viewing angle	θT (TOP)		CR > 10	—	85	—	Deg.	Note 3
Viewing angle	θB (BOTTOM)		CR > 10	—	85	—	Deg.	Note 3
Viewing angle	θL (LEFT)		CR > 10	—	85	—	Deg.	Note 3
Viewing angle	θR (RIGHT)		CR > 10	—	85	—	Deg.	Note 3
Luminance	L		IF = 40mA	—	300	—	cd/m²	Note 4

Notes (from document):

1. Response Time (Tg): Measured response time is determined by 10% to 90% brightness difference of rising (T_R) and falling (T_F) time.
2. Contrast Ratio (CR): Calculated as: CR = Luminance of LCD module with full screen white pattern (255,255,255) at center point / Luminance of LCD module with full screen Dark pattern (0,0,0) at center point.
3. Viewing Angle: Symmetrical 85 degrees typical in all directions (Top, Bottom, Left, Right) due to IPS technology, measured where Contrast Ratio exceeds 10.
4. Luminance: Measured at the center point of the panel with a backlight drive current of 40 mA. The luminance specification is 300 cd/m² (without CTP).
5. Color Chromaticity: The color chromaticity coordinates specified shall be calculated from the spectral data measured with all pixels first in red, green, blue and white. Measurements shall be made at the center of the panel.

3.4 Backlight Circuit

The document includes a backlight circuit note indicating:

• 16 LEDs (KA.K16颗灯)
• IF = 40 mA
• VF = 24V → 25.6V

3.5 Version Record

Version	Revise Date	Page	Content
00	—	ALL	New released

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4. Application Guidelines & Critical Notes

Intended Use

• High-end smartphones and feature phones
• Portable media players and handheld devices
• Industrial PDAs and mobile terminals
• In-vehicle display systems
• Wearable computing devices
• Any application requiring an HD+ resolution display with IPS viewing angles and a modern MIPI DSI interface

Critical Design Considerations

1. MIPI DSI Host Required – CRITICAL:

   • This module requires a host processor, GPU, or bridge chip with a MIPI DSI transmitter.
   • The ILI9881C-05 driver supports multiple data lane configurations (2-lane, 3-lane, or 4-lane). Based on the timing tables, the module can operate with up to 4 lanes.
   • The maximum bit rate per lane is 850 Mbps (for RGB 888 in 2-lane mode) – ensure your host transmitter can achieve this speed.

2. High-Voltage Backlight Driver – CRITICAL:

   • The backlight consists of 16 LEDs in series, requiring a forward voltage of 24V to 25.6V at 40 mA.
   • A boost-type constant-current LED driver is required to step up the system voltage (typically 3.3V-5V) to the required 24V+.
   • The total backlight power consumption is approximately 1W (24V x 40mA), which requires proper thermal management.

3. Power Supply Requirements:

   • Provide stable VCC (up to 7.0V absolute max) for main logic. The typical operating voltage is likely around 2.8V-3.3V (based on similar ILI9881C-based modules).
   • Provide stable IOVCC (1.8V typical, 3.8V max) for the I/O interface.
   • The VCC absolute maximum of 7.0V is unusual for LCD modules – double-check the specific recommended operating conditions in the full specification.

4. Signal Integrity for MIPI DSI:

   • The MIPI differential pairs (D0P/N, D1P/N, D2P/N, D3P/N, CLKP/CLKN) run at high speed.
   • On the host PCB: Ensure 100Ω differential impedance for each pair.
   • Length matching: Match trace lengths within each differential pair to within 0.5mm.
   • Skew matching: Match the lengths across all data lanes and the clock lane.
   • Grounding: Ensure solid ground planes beneath MIPI traces for proper return current paths.

5. Power On/Off Sequence:

   • Follow the standard ILI9881C power sequence: IOVCC → VCC → RESET → MIPI Data/Clock → Backlight.
   • For power-down: Backlight → MIPI Data/Clock → VCC → IOVCC.
   • The proper sequence is critical to prevent DC charge from being applied directly to the LCD panel.

6. Reset Circuit:

   • The RESX pin must be driven low for at least 10 µs to trigger a reset.
   • A pulse shorter than 5 µs will be rejected.
   • The reset recovery time is 5 ms (in Sleep In mode) or up to 120 ms (if reset occurs during Sleep Out mode).

7. Video Mode Timing Configuration:

   • Configure your host's display controller with the following parameters for the video stream:
     • Vertical: VSA=2, VBP=14, VFP=8, VACT=1280
     • Horizontal: HSA=2, HACT=720, HBP+HSA+HFP ≥ 1.6 µs
   • The timing tables indicate a resolution of 720x1280 active lines per frame, which matches the 720x1440 resolution when accounting for the display driver's internal configuration. (Note: The document has VACT = 1280 lines, while the resolution is 720(RGB)×1440. These are the active video timing parameters; the actual vertical resolution is derived from the display driver's register settings.)

8. Temperature Limits:

   • Operating Temperature: -20°C to +70°C.
   • Storage Temperature: -30°C to +80°C.

9. Mechanical Integration:

   • The module uses a 40-pin FPC – ensure the connector is properly aligned and the FPC is not bent sharply.
   • The module includes a backlight unit with a total thickness that should be accommodated in the enclosure design.
   • General tolerance is ±0.20 mm – account for this in mechanical design.

Handling & Compliance

• All materials must comply with ROHS and halogen-free standards.
• Observe stringent ESD precautions – the module uses CMOS LSI drivers.
• The module contains fragile glass – handle with care.
• Avoid electrostatic discharge on the FPC connector and driver IC area.
• Do not touch the COG's patterning area or LSI chips, as this may cause circuit damage or inner lead connection problems.
• Do not operate or store the LCD module outside the specified environmental conditions.

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5. Conclusion & Design-In Support

The LSI0593HD-MP027 specification details a high-performance 5.93-inch HD+ IPS display module with the ILI9881C-05 driver and a MIPI DSI interface.

Key Strengths:

1. High Resolution (720x1440): HD+ resolution in a compact 5.93-inch form factor, providing excellent pixel density for smartphones and handheld devices.
2. IPS Technology: 85-degree viewing angles in all directions ensure consistent image quality from any perspective.
3. High Contrast Ratio (1000:1): Excellent image depth and readability.
4. Modern MIPI DSI Interface: Supports multiple lane configurations (up to 4 lanes) with very high data rates (up to 850 Mbps per lane), enabling smooth video playback and fast screen updates.
5. Comprehensive MIPI Timing Specifications: The document provides detailed timing parameters for clock channels, data lanes, low-power mode transitions, and video mode configurations, essential for proper driver development.
6. Robust Temperature Range: Designed for -20°C to +70°C operation, suitable for industrial and mobile applications.
7. ROHS & Halogen-Free Compliance: Environmentally friendly.

Main Design Focus:

• The most critical design task is implementing a high-voltage (24V) constant-current LED backlight driver for the 16-series LED configuration.
• MIPI DSI Signal Integrity: Proper PCB layout with controlled impedance (100Ω differential) and length matching is essential at the high data rates (up to 850 Mbps per lane).
• Driver Software: Software engineers must carefully initialize the ILI9881C-05 driver IC via MIPI commands, configure the correct video mode timing parameters, and implement the power sequencing logic.
• Power Management: Provide stable VCC (3.3V), IOVCC (1.8V), and the 24V backlight supply, with proper sequencing.
• Mechanical Integration: Design the enclosure to accommodate a 5.93-inch display with a 40-pin FPC connector.

This module is an excellent choice for mid-to-high-end portable and embedded applications requiring a large, high-resolution display with wide viewing angles, modern high-speed interface, and proven driver IC support.